ICS9250-27 Datasheet, PDF (13/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III^TM
General I²C serial interface information
The information in this section assumes familiarity with I²C programming.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 _(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
How to Write:
Controller (Host)
Start Bit
A ddres s
D2_{(H )}
ICS (Slave/Receiver)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 _(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
A ddres s
D3_{(H )}
ICS (Slave/Receiver)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 2
Byte 3
Byte 4
Byte 5
Notes:
1.
The ICS clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
IDT^TM Frequency Generator and Integrated Buffers for Celeron & PII/III^TM
13
0395F—01/25/10