ICS8735-21 Datasheet, PDF (7/20 Pages) List of Unclassifed Manufacturers – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 6. AC Characteristics, V_CC = V_CCA = V_CCO = 3.3V ± 5%, V_EE = 0V, T_A = 0°C to 70°C
Parameter Symbol
Test Conditions
Minimum
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
PLL_SEL = 0V, f ≤ 700MHz
3.0
PLL_SEL = 0V
tsk(Ø)
Static Phase Offset; NOTE 3, 4
PLL_SEL = 3.3V
-50
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 3, 5
tjit(θ)
Phase Jitter; NOTE 3, 5, 6
t_L
PLL Lock Time
t_R / t_F
Output Rise/Fall Time; NOTE 7
20% to 80% @ 50MHz
300
odc
Output Duty Cycle
47
Typical
50
Maximum
700
4.2
20
150
25
±50
1
700
53
Units
MHz
ns
ps
ps
ps
ps
ms
ps
%
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions,
when the PLL is locked and the input reference frequency is stable.
NOTE 5: Characterized at VCO frequency of 622MHz.
NOTE 6: Phase jitter is dependent on the input source used.
IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
7
ICS8735AM-21 REV. A JULY 31, 2008