ICS8735-21 Datasheet, PDF (13/20 Pages) List of Unclassifed Manufacturers – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Schematic Example
Figure 5 shows a schematic example of the ICS8735-21. In this
example, the input is driven by an HCSL driver. The zero delay
buffer is configured to operate at 155.52MHz input and 77.75MHz
output. The logic control pins are configured as follows:
SEL [3:0] = 0101; PLL_SEL = 1
The decoupling capacitors should be physically located near the
power pin. For ICS8735-21.
3.3V
HCSL
VCC
Zo = 50 Ohm
Zo = 50 Ohm
(155.5 MHz)
VCC
SEL2
R8
R9
50
50
U1
1
2 ^CLK
3
4
5
6
nCLK
MR
VCCI
nFB_IN
7 ^FB_IN
8
9
10
SEL2
VEE
nQFB
QFB
R1
R2
ICS8735-21
50
50
RU3 RU4 RU5 RU6 RU7
1K
1K
SP
1K
SP
R3
PLL_SEL
50
SEL0
SEL1
SEL2
SEL3
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
SP = Space (i.e. not intstalled)
VCC=3.3V
SEL[3:0] = 0101,
Divide by 2
20
nc ₁₉
SEL1
SEL1
SEL0
VCCI
PLL_SEL
18
17
16
15
SEL0
VCC
PLL_SEL
VCCA
VCCA ₁₄
SEL3
SEL3
VCCO
Q
nQ
13
12
11
VCC
VCCA
C11
0.01u
R7
10
C16
10u
Zo = 50 Ohm
Zo = 50 Ohm
(77.75 MHz)
R4
50
VCC
+
-
LVPECL_input
R5
50
Bypass capacitors located
near the power pins
R6
50
(U1-4) VCC (U1-17) (U1-13)
C1
0.1uF
C2
0.1uF
C3
0.1uF
Figure 5. ICS8735-21 LVPECL Buffer Schematic Example
IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
13
ICS8735AM-21 REV. A JULY 31, 2008