ICS8735-21 Datasheet, PDF (1/20 Pages) List of Unclassifed Manufacturers – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

700MHz, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
ICS8735-21
General Description
The ICS8735-21 is a highly versatile 1:1 Differential-
ICS
to-3.3V LVPECL clock generator and a member of
HiPerClockS™ _{the HiPerClockS™family of High Performance Clock}
Solutions from IDT. The CLK, nCLK pair can accept
most standard differential input levels. The
ICS8735-21 has a fully integrated PLL and can be configured as
zero delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 700MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
Block Diagram
PLL_SEL ^Pullup
CLK ^Pulldown
nCLK ^Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
0
1
Features
• One differential 3.3V LVPECL output pair
One differential feedback output pair
• Differential CLK/nCLK input pair
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 25ps (maximum)
• Static phase offset: 50ps ± 100ps
• Full 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignments _{CLK 1}
nCLK 2
MR 3
VCC 4
nFB_IN 5
FB_IN 6
SEL2 7
VEE 8
nQFB 9
QFB 10
20 nc
19 SEL1
18 SEL0
17 VCC
16 PLL_SEL
15 VCCA
14 SEL3
13 VCCO
12 Q
11 nQ
ICS8735-21
Q
20-Lead SOIC
nQ
7.5mm x 12.8mm x 2.3mm package body
M Package
QFB
nQFB
Top View
PLL
FB_IN ^Pulldown
nFB_IN ^Pullup
SEL0 ^Pulldown
SEL1 ^Pulldown
SEL2 ^Pulldown
SEL3 ^Pulldown
MR ^Pulldown
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0
SEL1
nc
nc
CLK
nCLK
32 31 30 29 28 27 26 25
1
24
2
ICS8735-21
23
32-Lead VFQFN
3_{5mm x 5mm x 0.925mm}22
4
package body ²¹
5
K Package
20
6
Top View
19
VCCO
nc
Q
nQ
QFB
nQFB
nc 7
18 nc
MR 8
17 VCCO
9 10 11 12 13 14 15 16
IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
1
ICS8735AM-21 REV. A JULY 31, 2008