ICS8735-21 Datasheet, PDF (18/20 Pages) List of Unclassifed Manufacturers – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Package Outline - K Suffix for 32 Lead VFQFN
Ind exArea
N
To p View
S eating Plan e
A1
Anvil
Singula tion
OR
A3 ^L
E 2 _E2
2
(N -1)x e
(R ef.)
(Ref.)
N &N
Even
N
e (Ty p.)
2 _{If N & N}
1 ^{are Even}
2
(N -1)x e
(Re f.)
b
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
A
0. 08 C
e
(Ref.)
N &N
Odd
C
D2
2
D2
Th er mal
Ba se
The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package
dimensions are in Table 9B below.
Table 9B. Package Dimensions for 32 Lead VFQFN
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
N_D & N_E
D&E
8
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
18
ICS8735AM-21 REV. A JULY 31, 2008