ICS8735-21 Datasheet, PDF (15/20 Pages) List of Unclassifed Manufacturers – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8735-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8735-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{CC_MAX} = 3.465V * 150mA = 519.8mW
• Power (outputs)_MAX = 30mW/Loaded output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power__MAX = (3.465V, with all outputs switching) = 519.8mW + 60mW = 579.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 83.2°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.580W * 83.2°C/W = 118.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7A. Thermal Resistance θ_JA for 20 Lead SOIC, Forced Convection
θ_JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 7B. Thermal Resistance θ_JA for 32 Lead VFQFN, Forced Convection
θ_JA by Velocity
Meters per Second
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
2.5
29.0°C/W
IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
15
ICS8735AM-21 REV. A JULY 31, 2008