ICS87004I Datasheet, PDF (7/15 Pages) Integrated Device Technology – Output frequency range

ICS87004I Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 5A. AC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
f_MAX
t_PD
Output Frequency
Propagation Delay;
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V, f ≤ 250MHz,
Qx ÷ 2
t(Ø)
Static Phase Offset; ^{CLK0, nCLK0}
NOTE 2, 4
CLK1, nCLK1
PLL_SEL = 3.3V,
f_REF ≤ 167MHz, Qx ÷ 1
tsk(o)
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V
tjit(cc)
t_L
t_R / t_F
odc
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
f_OUT > 40MHz
20% to 80%
Minimum
15.625
5
-100
-200
400
40
Typical
50
-75
40
30
50
Maximum
250
6.2
200
200
65
45
1
800
60
Units
MHz
ns
ps
ps
ps
ps
ms
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, V_DD = V_DDO = 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
f_MAX
t_PD
Output Frequency
Propagation Delay;
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V, f ≤ 250MHz,
Qx ÷ 2
t(Ø)
Static Phase Offset; ^{CLK0, nCLK0}
NOTE 2, 4
CLK1, nCLK1
PLL_SEL = 2.5V,
f_REF ≤ 167MHz, Qx ÷ 1
tsk(o)
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V
tjit(cc)
t_L
t_R / t_F
odc
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
f_OUT > 40MHz
20% to 80%
Minimum
15.625
5.3
-250
-350
400
43
Typical
-25
-150
40
35
50
Maximum
250
6.9
150
150
65
45
1
700
57
Units
MHz
ns
ps
ps
ps
ps
ms
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS87004AGI REVISION D JANUARY 4, 2010
7
©2009 Integrated Device Technology, Inc.