ICS87004I Datasheet, PDF (2/15 Pages) Integrated Device Technology – Output frequency range

ICS87004I Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 12, 21
2, 20,
22, 24
3, 19, 23
4, 5,
6, 7
8
9
10
11
13
14
15
16
17
18
Name
GND
Q0, Q3,
Q2, Q1
V_DDO
SEL0, SEL1,
SEL2, SEL3
CLK_SEL
V_DD
CLK0
nCLK0
V_DDA
nCLK1
CLK1
PLL_SEL
FB_IN
MR
Type
Power
Output
Power
Description
Power supply ground.
Single-ended clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Input
Power
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Clock select input. When HIGH, selects differential CLK1, nCLK1. When LOW,
selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels.
Core supply pin.
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating.
Analog supply pin.
Inverting differential clock input. V_DD/2 default when left floating.
Non-inverting differential clock input.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
C_PD
Power Dissipation
Capacitance (per output)
R_OUT
Output Impedance
Test Conditions
V_DD, V_DDO = 3.465V
V_DD, V_DDO = 2.625V
Minimum
Typical
4
51
51
5
7
Maximum
23
17
12
Units
pF
kΩ
kΩ
pF
pF
Ω
ICS87004AGI REVISION D JANUARY 4, 2010
2
©2009 Integrated Device Technology, Inc.