ICS87004I Datasheet, PDF (1/15 Pages) Integrated Device Technology – Output frequency range

1:4, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
ICS87004I
DATA SHEET
General Description
The ICS87004I is a highly versatile 1:4 Differential-
ICS
to-LVCMOS/LVTTL Clock Generator. The ICS87004I
HiPerClockS™ _{has two selectable clock inputs. The CLK0, nCLK0}
and CLK1, nCLK1 pairs can accept most standard
differential input levels. Internal bias on the nCLK0 and
nCLK1 inputs allows the CLK0 and CLK1 inputs to accept
LVCMOS/LVTTL. The ICS87004I has a fully integrated PLL and can
be configured as a zero delay buffer, multiplier or divider and has an
input and output frequency range of 15.625MHz to 250MHz. The
reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
• CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL
levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration with
configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 65ps (maximum)
• Static phase offset: 50ps ± 150ps (3.3V ± 5%), CLK0/nCLK0
• Full 3.3V or 2.5V output operating supply
• 5V tolerant
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
PLL_SEL ^Pullup
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
0
Q0
CLK0 ^Pulldown
nCLK0 ^{Pullup/Pulldown}
0
1
Q1
CLK1 ^Pulldown
nCLK1 ^{Pullup/Pulldown}
1
PLL
Q2
CLK_SEL ^Pulldown
FB_IN ^Pulldown
8:1, 4:1, 2:1, 1:1,
Q3
1:2, 1:4, 1:8
GND 1
Q0 2
VDDO 3
SEL0 4
SEL1 5
SEL2 6
SEL3 7
CLK_SEL 8
VDD 9
CLK0 10
nCLK0 11
GND 12
24 Q1
23 VDDO
22 Q2
21 GND
20 Q3
19 VDDO
18 MR
17 FB_IN
16 PLL_SEL
15 CLK1
14 nCLK1
13 VDDA
ICS87004I
SEL0 ^Pulldown
SEL1 ^Pulldown
24-Lead TSSOP
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
SEL2 ^Pulldown
SEL3 ^Pulldown
MR ^Pulldown
ICS87004AGI REVISION D JANUARY 4, 2010
1
©2009 Integrated Device Technology, Inc.