DT8SLVD1204I Datasheet, PDF (7/18 Pages) Integrated Device Technology – Two selectable differential clock input pairs

Parameter Measurement Information
V_DD
LVDS Output Load Test Circuit
V_DD
nPCLK[0:1]
PCLK[0:1]
GND
Differential Input Level
nPCLK[0:1]
PCLK[0:1]
nQy
Qy
t _PLH
t _PHL
tsk(p)= |t_PHL - t_PLH|
Pulse Skew
nQx
Qx
nQy
Qy
Output Skew
IDT8SLVD1204I DATA SHEET
Part 1
nQx
Qx
Part 2
nQy
Qy
t sk(pp)
Part-to-Part Skew
nQ[0:3]
Q[0:3]
20%
80%
t_R
Output Rise/Fall Time
80%
t_F
V_OD
20%
REVISION A 07/10/14
7
2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V