DT8SLVD1204I Datasheet, PDF (2/18 Pages) Integrated Device Technology – Two selectable differential clock input pairs

IDT8SLVD1204I DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
GND
Power
Power supply ground.
2
SEL
Input
Pullup/ Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
Pulldown _{interface levels.}
3
PCLK1
Input
Pulldown Non-inverting differential clock/data input.
4
nPCLK1
Input
Pullup/
Pulldown
Inverting differential clock/data input. V_DD/2 default when left floating.
5
V_DD
Power
Power supply pin.
6
PCLK0
Input
Pulldown Non-inverting differential clock/data input.
7
nPCLK0
Input
Pullup/
Pulldown
Inverting differential clock/data input. V_DD/2 default when left floating.
8
9, 10
V_REF
Q0, nQ0
Output
Output
Bias voltage reference for the PCLK, nPCLK inputs.
Differential output pair 0. LVDS interface levels.
11, 12
Q1, nQ1
Output
Differential output pair 1. LVDS interface levels.
13, 14
Q2, nQ2
Output
Differential output pair 2. LVDS interface levels.
15, 16
Q3, nQ3
Output
Differential output pair 3. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table
Input
SEL
Operation
0
PCLK0, nPCLK0 is the selected differential clock input.
1
PCLK1, nPCLK1 is the selected differential clock input.
Open (default) Input buffers are disabled and outputs are static.
NOTE: SEL is an asynchronous control.
2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V
2
REVISION A 07/10/14