DT8SLVD1204I Datasheet, PDF (1/18 Pages) Integrated Device Technology – Two selectable differential clock input pairs

2:4, LVDS Output Fanout Buffer, 2.5V
IDT8SLVD1204I
DATA SHEET
General Description
The IDT8SLVD1204I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8SLVD1204I is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVD1204I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 300ps (maximum)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
10kHz - 20MHz: 95fs (maximum)
• Full 2.5V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
VDD
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
GND GND
0
VDD
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
1
GND GND
VDD
Pin Assignment
Q0
nQ0
12 11 10 9
Q2 13
8 VREF
nQ2 14
7 nPCLK0
Q3 15
6 PCLK0
nQ3 16
5 VDD
1 23 4
Q1
nQ1
IDT8SLVD1204I
16 lead VFQFN
Q2
3.0mm x 3.0mm x 0.9mm package body
1.7mm x 1.7mm ePad
nQ2
NL Package
Top View
Q3
nQ3
SEL ^{Pullup/Pulldown}
V_REF
GND
Reference
Voltage
Generator
IDT8SLVD1204I REVISION A 07/10/14
1
©2014 Integrated Device Technology, Inc.