DT8SLVD1204I Datasheet, PDF (10/18 Pages) Integrated Device Technology – Two selectable differential clock input pairs

IDT8SLVD1204I DATA SHEET
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, and other differential
signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
LVPECL
2.5V
2.5V
PCLK
nPCLK
LVPECL
Input
Figure 2A. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 2B. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
PCLK
nPCLK
Figure 2C. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
2:4, LVDS OUTPUT FANOUT BUFFER, 2.5V
10
REVISION A 07/10/14