82P33731_16 Datasheet, PDF (64/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
8.5 INPUT / OUTPUT CLOCK TIMING
The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.
Input Clock
Output Clock
t1
Figure 33. Input / output clock timing
Table 40: Input-to-Output Delay via APLL1/2
Output
t₁ Min (ns)
t₁ Max (ns)
t₁ Range (ns_pp)
Any LVCMOS Input to any of OUT01, OUT02 or
OUT07
13
19
6
(±3 around mean)
Any LVPECL/LVDS Input to any of OUT03, OUT04
OUT05 or OUT06
11.5
16.5
5
(±2.5 around mean)
Any Input to any APLL1/2 Output
10
19
9
(±4.5 around mean)
Any Input to [M]FRSYNC Output
0
8
8
(typical value is 2.5ns)
NOTE 1. The measurements in the above table takes into account any delays in the clock path from any input to any output; through either DPLL1 or DPLL2 and the
APLL either APLL1 or APLL2.
NOTE 2. The measurements in the above table are over operational temperature, varying power supply and repeated power on/off cycle.
NOTE 3. Measurements are taken using an ideal REF input and an ideal System clock to account for only internal delays in the device.
8.6 OUTPUT / OUTPUT CLOCK TIMING
Output Clock
t1
Output Clock
Figure 34. Output / output clock timing
Table 41: APLL1/2 Output-to-Output Delay
Output
Output-to-Output, LVCMOS
(OUT01 to OUT02)
Output-to-Output, LVPECL/LVDS
Input to a LVPECL/LVDS Output
(OUT03 to OUT04 or OUT05 to OUT06)
t₁ Min (ps)
-110
-85
t₁ Max (ps)
110
85
©2016 Integrated Device Technology, Inc.
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Revision 5, December 8, 2016