82P33731_16 Datasheet, PDF (3/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
HIGHLIGHTS ........................................................................................................................................................................... 5
FEATURES .............................................................................................................................................................................. 5
APPLICATIONS....................................................................................................................................................................... 5
DESCRIPTION......................................................................................................................................................................... 6
FUNCTIONAL BLOCK DIAGRAM .......................................................................................................................................... 7
1 PIN ASSIGNMENT ............................................................................................................................................................. 8
2 PIN DESCRIPTION ............................................................................................................................................................ 9
2.1 RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS ........................................................................................................... 12
2.1.1 Inputs .............................................................................................................................................................................................. 12
2.1.2 Outputs ........................................................................................................................................................................................... 12
2.2 RESET OPERATION ..................................................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 14
3.1 SYNCHRONOUS ETHERNET (SYNCE), SONET, AND SDH SYSTEM ARCHITECTURES ...................................................................... 14
3.2 HARDWARE FUNCTIONAL DESCRIPTION ................................................................................................................................................ 16
3.2.1 System clock .................................................................................................................................................................................. 16
3.2.2 Modes of operation ........................................................................................................................................................................ 16
3.2.2.1 DPLL1 Operating Mode ................................................................................................................................................... 16
3.2.2.1.1 Free-Run Mode ............................................................................................................................................. 18
3.2.2.1.2 Pre-Locked Mode .......................................................................................................................................... 18
3.2.2.1.3 Locked Mode ................................................................................................................................................. 18
3.2.2.1.4 Pre-Locked2 Mode ........................................................................................................................................ 20
3.2.2.1.5 Lost-Phase Mode .......................................................................................................................................... 20
3.2.2.1.6 DCO Control Modes ...................................................................................................................................... 20
3.2.2.1.7 Holdover Mode .............................................................................................................................................. 21
3.2.2.1.8 Hitless Reference Switching .......................................................................................................................... 21
3.2.2.1.9 Phase Slope Limit .......................................................................................................................................... 22
3.2.2.1.10 Frequency Offset Limit .................................................................................................................................. 22
3.2.2.2 DPLL2 Operating Mode ................................................................................................................................................... 22
3.2.2.2.1 Free-Run Mode ............................................................................................................................................. 22
3.2.2.2.2 Locked Mode ................................................................................................................................................. 22
3.2.2.2.3 Holdover Mode .............................................................................................................................................. 22
3.2.2.2.4 Frequency Offset Limit .................................................................................................................................. 23
3.2.3 Input Clocks and frame sync ........................................................................................................................................................ 23
3.2.3.1 Input Clock Pre-divider ..................................................................................................................................................... 23
3.2.3.2 Input Clock Quality Monitoring ......................................................................................................................................... 25
3.2.3.2.1 Loss of Signal (LOS) Monitoring .................................................................................................................... 25
3.2.3.2.2 Activity Monitoring ......................................................................................................................................... 25
3.2.3.2.3 Frequency Monitoring .................................................................................................................................... 26
3.2.3.3 Input Clock Selection ........................................................................................................................................................ 27
3.2.3.3.1 Forced Selection ............................................................................................................................................ 27
3.2.3.3.2 Automatic Selection ....................................................................................................................................... 27
3.2.3.3.2.1Input Clock Validation ................................................................................................................... 27
3.2.3.3.2.2Revertive and Non-Revertive Switching ....................................................................................... 28
3.2.3.3.3 Selected / Qualified Input Clocks Indication .................................................................................................. 28
3.2.3.3.4 Input Clock Loss of Signal ............................................................................................................................. 28
3.2.4 DPLL Locking Process .................................................................................................................................................................. 28
3.2.4.1 Fast Loss .......................................................................................................................................................................... 28
3.2.4.2 Fine Phase Loss ............................................................................................................................................................... 28
3.2.4.3 Hard Limit Exceeding ....................................................................................................................................................... 28
3.2.4.4 Locking Status .................................................................................................................................................................. 28
3.2.4.5 Phase Lock Alarm ............................................................................................................................................................ 29
3.2.5 APLL1 and APLL2 .......................................................................................................................................................................... 29
©2016 Integrated Device Technology, Inc.
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Revision 5, December 8, 2016