82P33731_16 Datasheet, PDF (32/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
Table 13: Outputs on OUT11~12
OUTn_ODSEL0/1[2:0]
(Output Divider)
SONET
(XTALn =
24.8832 MHz)
Outputs on OUT11~12¹
ETHERNET
(XTALn =
25 MHz)
ETHERNET * 66/64
(XTALn =
25.78125 MHz)
1
622.08 MHz
625 MHz
644.53125 MHz
2
311.04 MHz
312.5 MHz
322.265625 MHz
4
155.52 MHz
156.25 MHz
161.1328125 MHz
5
125 MHz
8²
77.76 MHz
25³
25 MHz
(OUTn_ENABLE = 0)
Output ‘n’ is disabled
(OUTn_ENABLE = 1)
Output ‘n’ is enabled
Note:
1. The blank cell means the configuration is reserved. The proper XTAL must be populated for XTAL1~2 based on the
selected mode.
2. OUT12 only
3. OUT11 only
OUT1 to OUT10 output clocks can be inverted by setting OUTn_IN-
VERT bit (0: output not inverted, 1: output inverted) in OUTn_MUX-
_CNFG register for (1 < n < 7), in OUT8_FREQ_CNFG register for
OUT8, and in OUT9_CNFG and OUT10_CNFG registers for OUT9 and
OUT10 respectively.
The output clocks can be squelched by setting OUT-
n_SQUELCH[1:0] bits (0x: no squelch, 10: squelch to '0', 11: squelch to
'1') in OUTn_MUX_CNFG register for (1 < n < 7), and in OUT9_CNFG
and OUT10_CNFG registers for OUT1 to OUT7, and OUT9 and OUT10
respectively.
OUT1 to OUT7 output clocks can be individually powered down by
setting OUTn_PDN bit to '1' in OUTn_MUX_CNFG register for (1 < n <
7)
OUT8 can be enabled or disabled by programming OUT8_PDN and
DPLL2_INPUT_FAIL bits in OUT8_FREQ_CNFG register.
OUT11 and OUT12 can be enabled or disabled by programming
OUT11_ENABLE and OUT12_ENABLE in the OUT11 and OUT2 config-
uration registers respectively.
82P33731 provides a variety of output frequencies from 1Hz to
650MHz.
APLL1 is always enabled and the default frequency for OUT1, OUT2,
and OUT3 is respectively 25 MHz, 125 MHz, and 156.25MHz. OUT4 is
squelched by default.
By default, OUT5 to OUT7 are squelched. Set the proper registers to
set desired frequency values for OUT5 to OUT7.
OUT8 is powered down by default.
DPLL3 is disabled by default, and if it is enabled, then the default fre-
quency for OUT9 and OUT10 is respectively 16.384 MHz and 2.048
MHz.
APLL1, APLL2, and the DPLLs can be configured from an external
EPROM after reset. It can be used to set specific start up frequency val-
ues as needed by the application.
OUT11 and OUT12 are powered down by default. APLL3 must be
configured via the I2C slave interface to set OUT11 and OUT12 fre-
quency values.
3.2.7.2 Frame Sync Signals
Either an 8 kHz or a 2 kHz frame sync, or a 1PPS sync signal are
output on the FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS pins if
enabled by the 8K_1PPS_EN and 2K_1PPS EN bits respectively. They
are CMOS outputs.
The output sync frequencies are independent of the input sync fre-
quency. The output FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS fre-
quencies are selected through the DPLL1_fr_mfr_sync_cnfg registers.
Any supported clock frequency at the clock input can be associated
with the sync signals.
The frame sync output signals are derived from the DPLL1 and
DPLL2 output and are aligned with the output clock. They are synchro-
nized to the frame sync input signal. In DCO control modes (section
3.2.2.1.6), the output FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS
must not be used, a 1PPS output sync signal can be generated in any of
the output clocks connected to the DCO being used.
The frame/sync output signals align to the first edge of the associ-
ated reference clock that occurs after the edge of the frame/sync input
signal. The frequency of the associated reference clock must be lower or
equal to the frequencies of the output clocks that requires to be aligned
with the frame/sync pulse signal.
©2016 Integrated Device Technology, Inc.
32
Revision 5, December 8, 2016