82P33731_16 Datasheet, PDF (24/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
Each Pre-divider consists of an FEC divider and a DivN divider,.
IN3~IN8 also include an HF (High Frequency) divider. Figure 9 shows a
block diagram of the pre-dividers for an input clock.
For 1 PPS, 2 kHz, 4 kHz or 8 kHz input clock frequency only, the Pre-
divider should be bypassed by setting INn_DIV[1:0] bits = “0” (3 < n < 8),
DIRECT_DIV bit = “0”, and LOCK_8K bit = “0”. The corresponding IN_-
FREQ[3:0] bits should be set to match the input frequency.
The HF divider, which is available for IN3 ~ IN8, should be used
when the input clock is higher than () 162.5 MHz. The input clock can
be divided by 4, 5 or can bypass the HF divider, as determined by the
INn_DIV[1:0] bits (3 < n < 8).
The DivN divider can be bypassed, as determined by the
DIRECT_DIV bit and the LOCK_8K bit. When DivN divider is bypassed,
the corresponding IN_FREQ[3:0] bits should be set to match the input
frequency. DIVN must be bypassed on a reference clock input that is
also associated with another reference input used as SYNC.
When the DivN divider is used for INn (3  n  14), the division factor
setting should observe the following order:
1. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
The division factor is calculated as follows:
Division Factor = (the frequency of the clock input to the DivN
divider ÷ the frequency of the DPLL required clock set by the IN_-
FREQ[3:0] bits) - 1
The Pre-divider configuration and the division factor setting depend
on the input clock on one of the IN3 ~ IN14 pins and the DPLL required
clock.
For the fractional input divider, the FEC divider, each input clock has
a 16-bit (fec_divp_cnfg[15:0]) that represents the value of the numerator
and a 16-bit (fec_divq_cnfg[15:0]) that represents the value of the
denominator of FEC divider. The FEC division factor is calculated as fol-
lows:
FEC Division Factor = (fec_divp_cnfg[15:0]) ÷
(fec_divq_cnfg[15:0])
Pre-Divider
INn_DIV[1:0] bits
3<n<8
Input Clock INn
3 < n < 14
HF Divider
(for IN3 ~ IN8)
1
FEC Divider (P/Q)
0
DIRECT_DIV bit
LOCK_8K bit
00
DPLL
Clock
DivN Divider
1< n < 19440
01
Figure 9. Pre-divider for an input clock
©2016 Integrated Device Technology, Inc.
24
Revision 5, December 8, 2016