82P33731_16 Datasheet, PDF (38/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
Table 14: Timing Definition for Standard Mode and Fast Mode⁽¹⁾
Symbol
Parameter
Standard Mode
Min
Max
Fast Mode
Unit
Min
Max
SCL Serial clock frequency
0
100
0
400
kHz
t_{HD; STA}
Hold time (repeated) START condition. After this period, the
first clock pulse is generated
4.0
-
0.5
-
s
t_LOW LOW period of the SCL clock
4.7
-
1.3
-
s
t_HIGH HIGH period of the SCL clock
4.0
-
0.6
-
s
t_{SU; STA} Set-up time for a repeated START condition
4.7
-
0.6
-
s
t_{HD; DAT}
Data hold time: for CBUS compatible masters for I²C-bus
devices
5.0
0⁽²⁾
-
3.45⁽³⁾
-
0⁽²⁾
-
0.9⁽³⁾
s
t_{SU; DAT} Data set-up time
250
-
100⁽⁴⁾
-
ns
t_r
Rise time of both SDA and SCL signals
-
1000
20 + 0.1Cb⁽⁵⁾
300
ns
t_f
Fall time of both SDA and SCL signals
-
300
20 + 0.1Cb⁽⁵⁾
300
ns
t_{SU; STO} Set-up time for STOP condition
4.0
-
0.6
-
s
t_BUF Bus free time between a STOP and START condition
4.7
-
1.3
-
s
C_b
Capacitive load for each bus line
-
400
-
400
pF
V_nL
Noise margin at the LOW level for each connected device
(Including hysteresis)
0.1VDD
-
0.1VDD
-
V
V_nH
Noise margin at the HIGH level for each connected device
(Including hysteresis)
0.2VDD
-
0.2VDD
-
V
t_sp
Pulse width of spikes which must be suppressed by the input
filter
0
50
0
50
ns
Note:
1. All values referred to V_IHmin and V_ILmax levels (see Table 23)
2. A device must Internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_{IHmin o}f the SCL signal) to bridge the undefined region of the fall-
ing edge of SCL.
3. The maximum t_{HD; DAT h}as only to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.
4. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t_{SU; DAT} ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t_rmax + t_{SU; DAT} = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-bus specification) before the SCL line is released.
5. C_b = total capacitance of one bus line in pF. If mixed with Hs-mode device, faster fall-times according to Table 24 allowed.
n/a = not applicable
©2016 Integrated Device Technology, Inc.
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Revision 5, December 8, 2016