ICS9LPRS464 Datasheet, PDF (6/23 Pages) Integrated Device Technology – System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs

ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT
PARAMETER
Crossing Point Variation
Frequency
Long Term Accuracy
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
CPU, DIF HTT Jitter - Cycle to
Cycle
Accumulated Jitter
SYMBOL
∆V_CROSS
f
ppm
S_RISE
S_FALL
t_SLVAR
CPUJ_C2C
t_JACC
CONDITIONS
Single-ended Measurement
Spread Specturm On
Spread Specturm Off
Differential Measurement
Differential Measurement
Single-ended Measurement
Differential Measurement
See Notes
MIN
198.8
-300
0.5
0.5
TYP
MAX
140
200
+300
10
10
20
150
1
Peak to Peak Differential Voltage V_D(PK-PK)
Differential Measurement
400
2400
Differential Voltage
Duty Cycle
V_D
Differential Measurement
200
D_CYC
Differential Measurement
45
1200
55
Amplitude Variation
∆V_D
Change in V_D DC cycle to cycle
-75
75
UNITS
mV
MHz
ppm
V/ns
V/ns
%
ps
ns
mV
mV
%
mV
NOTES
1,2,5
1,3
1,11
1,4
1,4
1
1,6
1,7
1,8
1,9
1
1,10
CPU Skew
CPU_SKEW10
Differential Measurement
100
ps
1
Guaranteed by design and characterization, not 100% tested in production.
Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not
important due to the blocking cap.
Minimum Frequency is a result of 0.5% down spread spectrum
Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec when
crossing through this region.
5 _{Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK}
and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
6 _{Max difference of tCYCLE between any two adjacent cycles.}
7 _{Accumulated tjc.over a 10 µs time period, measured with JIT2 TIE at 50ps interval.}
8 _{VD(PK-PK) is the overall magnitude of the differential signal.}
9 _{VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD.}
VD(max) is the largest amplitude allowed.
10 _{The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of}
the signal.
11 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz}
IDT^TM/ICS^TM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
6
1377A—04/07/08