ICS9LPRS464 Datasheet, PDF (5/23 Pages) Integrated Device Technology – System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs

ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
Absolute Max
PARAMETER
3.3V Core Supply Voltage
SYMBOL
VDD_A
CONDITIONS
-
MIN
TYP
3.3V Logic Input Supply
Voltage
VDD_In
-
Storage Temperature
Ts
-
Ambient Operating Temp Tambient
-
Case Temperature
Tcase
-
Input ESD protection HBM ESD prot
-
GND -
0.5
-65
0
2000
1_{Guaranteed by design and characterization, not 100% tested in production.}
MAX
V_DD + 0.5V
V_DD + 0.5V
150
70
115
UNITS
V
V
°_C
°C
°C
V
Notes
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
V_{IH_FS}
3.3 V +/-5%
2
3.3 V +/-5%
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up
resistors
V_SS - 0.3
-5
-5
V_IN = 0 V; Inputs with pull-up
resistors
-200
3.3 V +/-5%
0.7
V_{IL_FS}
I_DD3.3OP
3.3 V +/-5%
9LPRS462, all outputs driven
9LPRS464, all outputs driven
V_SS - 0.3
V_DD + 0.3
V
1
0.8
V
1
5
uA
1
uA
1
uA
1
V_DD + 0.3
V
1
0.35
V
1
200
mA
1
180
mA
1
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
I_DD3.3PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_STAB
all diff pairs low/low
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-
assertion of PD to 1st clock
21
14.31818
7
5
6
5
1.8
Modulation Frequency
Triangular Modulation
30
33
Tdrive_PD
CPU output enable after
PD de-assertion
300
Tfall_PD
PD fall time of
5
Trise_PD
PD rise time of
5
mA
1
MHz
2
nH
1
pF
1
pF
1
pF
1
ms
1
kHz
1
us
1
ns
1
ns
1
SMBus Voltage
V_DD
2.7
5.5
V
1
Low-level Output Voltage
V_OL
@ I_PULLUP
Current sinking at
V_OL = 0.4 V
I_PULLUP
4
SMBCLK/SMBDAT
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
0.4
1000
V
1
mA
1
ns
1
SMBCLK/SMBDAT
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL}
outputs.
IDT^TM/ICS^TM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
1377A—04/07/08
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