ICS9LPRS464 Datasheet, PDF (15/23 Pages) Integrated Device Technology – System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs

ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
SMBus Table: Spread Spectrum Enable and CPU Frequency Select Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Pin #
-
-
-
-
-
-
-
Name
FS Source
ATIG SS_EN
SRC SS_EN
CPU SS_EN
CPU FS3
CPU FS2
CPU FS1
Control Function
Latched Input or SMBus
Frequency Select
ATIG Spread Spectrum Enable
SRC Spread Spectrum Enable
CPU Spread Spectrum Enable
CPU Freq Select Bit 3
CPU Freq Select Bit 2
CPU Freq Select Bit 1
Type
RW
RW
RW
RW
RW
RW
RW
Bit 0
-
CPU FS0
CPU Freq Select Bit 0
RW
Note: Each Spread Spectrum Enable bit is independent from the other.
Bit(6:4) must all set to "1" in order to enable spread for CPU, SRC and ATIG clocks.
0
Latched
Inputs
Disable
Disable
Disable
1
SMBus
Enable
Enable
Enable
See Table 1:
CPU Frequency Selection
Table
PWD
0
0
0
0
0
Latch
Latch
Latch
SMBus Table: Output Control Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Pin #
7
6
54
55
56
51
44,43
Name
48MHz_1
48MHz_0
REF2
REF1
REF0
HTTCLK0
CPUCLK1
Bit 0 48,47
CPUCLK0
Control Function
48MHz_1 Output Enable
48MHz_0 Output Enable
REF2 Output Enable
REF1 Output Enable
REF0 Output Enable
HTTCLK0 Output Enable
CPUCLK1 Output Enable
CPUCLK0 Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: ATIGCLK and CLKREQB# Output Control Register
Byte 2 Pin #
Name
Control Function
Bit 7
Reserved
Bit 6
Reserved
Bit 5 31,30
ATIGCLK1
ATIGCLK1 Output Enable
Bit 4 35,34
ATIGCLK0
ATIGCLK0 Output Enable
Bit 3 20,21
REQBSRC2
CLKREQB# Controls SRC2
Bit 2
Reserved
Bit 1 24,25
REQBSRC1
CLKREQB# Controls SRC1
Bit 0
Reserved
Type
RW
RW
RW
RW
0
Disable
Disable
Does not
control
Does not
control
1
Enable
Enable
Controls
Controls
PWD
0
0
1
1
0
0
0
0
SMBus Table: SRCCLK Output Control Register
Byte 3 Pin #
Name
Control Function
Bit 7 12,13
SRCCLK5
Bit 6 16,17
SRCCLK4
Bit 5
Bit 4
Bit 3
Bit 2
18,19
20,21
24,25
SRCCLK3
SRCCLK2
Reserved
SRCCLK1
Master Output control. Enables
or disables output, regardless of
CLKREQ# inputs.
Bit 1
Reserved
Bit 0 39,38
SRCCLK0
Type
RW
RW
RW
RW
-
RW
-
RW
0
Disable
Disable
Disable
Disable
-
Disable
-
Disable
1
Enable
Enable
Enable
Enable
-
Enable
-
Enable
PWD
1
1
1
1
1
1
1
1
IDT^TM/ICS^TM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
15
1377A—04/07/08