ICS952601 Datasheet, PDF (6/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

ICS952601
Programmable Timing Control Hub^TM for Next Gen P4^TM Processor
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
T_A = 0 - 70°C; V_DD = 3.3 V +/-5%; C_L =2pF
PARAMETER
SYMBOL
Current Source Output
Impedance
Zo¹
CONDITIONS
V_O = V_x
MIN
3000
TYP
MAX
UNITS NOTES
Ω
1
Voltage High
Voltage Low
VHigh
Statistical measurement on
660
770 850
1
single ended signal using
mV
VLow
oscilloscope math function.
-150
5
150
1
Max Voltage
Min Voltage
Vovs
Measurement on single ended
756 1150
mV
1
Vuds
signal using absolute value.
-300
-7
1
Crossing Voltage (abs) Vcross(abs)
250
350 550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
12
140
mV
1
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
200MHz nominal
4.9985 5.0000 5.0015 ns
2
200MHz spread
4.9985
5.0266 ns
2
166.66MHz nominal
5.9982 6.0000 6.0018 ns
2
Average period
Tperiod
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
5.9982
6.0320 ns
2
7.4978 7.5000 7.5023 ns
2
7.4978
5.4000 ns
2
9.9970 10.0000 10.0030 ns
2
100.00MHz spread
9.9970
10.0533 ns
2
Absolute min period
T_absmin
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
4.8735
5.8732
7.3728
9.8720
ns
1,2
ns
1,2
ns
1,2
ns
1,2
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
t_r
V_OL = 0.175V, V_OH = 0.525V
175
332 700
ps
1
t_f
V_OH = 0.525V V_OL = 0.175V
175
344 700
ps
1
d-t_r
30
125
ps
1
d-t_f
30
125
ps
1
d_t3
Measurement from differential
wavefrom
45
49
55
%
1
Skew
t_sk3
V_T = 50%
8
100
ps
1
Jitter, Cycle to cycle
t_jcyc-cyc
Measurement from differential
wavefrom
37
125
ps
1
1_{Guaranteed by design, not 100% tested in production.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at}
14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
IDT^TM Progammable Timing Control Hub^TM for Next Gen P4^TM Processor
6
701J—01/25/10