ICS952601 Datasheet, PDF(14/25 Page) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

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ICS952601 Datasheet, PDF (14/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

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ICS952601

Programmable Timing Control HubTM for Next Gen P4TM Processor

PCI Stop Functionality

The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to

be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the

PCI_STOP register bit.

PCI_STOP# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT

REF Note

Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz

Normal Normal Iref * 6 Low 66MHz Low

48MHz 14.318MHz

or Float

PCI_STOP# Assertion (transition from '1' to '0')

The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all

PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,

the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and

the SRC# will latch low as shown below.

Tsu

PCI_STOP#

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# - De-assertion

The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After

detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free

manner.

Tsu

PCI_STOP#

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

Tdrive_SRC

IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor

701Jâ01/25/10

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