ICS952601 Datasheet, PDF (19/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

ICS952601
Programmable Timing Control Hub^TM for Next Gen P4^TM Processor
CPU Clock Tristate Timing
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
1.8mS
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
1.8mS
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
IDT^TM Progammable Timing Control Hub^TM for Next Gen P4^TM Processor
19
701J—01/25/10