ICS952601 Datasheet, PDF (3/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

ICS952601
Programmable Timing Control Hub^TM for Next Gen P4^TM Processor
Pin Description (continued)
PIN
#
PIN NAME
29 3V66_4/VCH
30 SDATA
31 48MHz_USB
32 48MHz_DOT
33 GND
34 VDD48
35 Vtt_PWRGD#
36 VDD
37 SRCCLKC
38 SRCCLKT
39 GND
40 CPUCLKC0
41 CPUCLKT0
42 VDDCPU
43 CPUCLKC1
44 CPUCLKT1
45 GND
46 CPUCLKC2
47 CPUCLKT2
48 VDDCPU
49 PCI_STOP#
50 CPU_STOP#
51 FS_A
52 IREF
53 GND
54 GNDA
55 VDDA
56 FS_B
PIN TYPE
DESCRIPTION
OUT
I/O
OUT
OUT
PWR
PWR
IN
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
IN
OUT
PWR
PWR
PWR
IN
66.66MHz clock output for AGP support. AGP-PCI should be
aligned with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for SMBus circuitry, 5V tolerant.
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at
logic 0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
Stops all CPUCLK besides the free running clocks. Internal pull-up
of 150K nominal
Frequency select pin, see Frequency table for functionality
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied
to ground in order to establish the appropriate current. 475 ohms is
the standard value.
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
IDT^TM Progammable Timing Control Hub^TM for Next Gen P4^TM Processor
3
701J—01/25/10