ICS952601 Datasheet, PDF (5/25 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Next Gen P4™ processor

ICS952601
Programmable Timing Control Hub^TM for Next Gen P4^TM Processor
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5 VDD + 0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase1
Case Temperature 1
115
°C
Tcase2
Case Temperature 2
94
°C
ESD prot Input ESD protection human body model
2000
V
1. This case temperature limits the junction temperature to <150 °C for package reliabilty
2. This case temperature limits the junction temperature to <125 °C for long term silicon reliability
Notes
1
2
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
V_MID
V_IL
I_IH
I_IL1
I_IL2
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-
up resistors
V_IN = 0 V; Inputs with pull-up
resistors
2
1
V_SS - 0.3
-5
-5
-200
MAX UNITS NOTES
V_DD + 0.3 V
1.8
V
0.8
V
5
uA
uA
uA
Operating Supply Current
I_DD3.3OP
Full Active, C_L = Full load;
350
mA
258
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
29
35
mA
0.3
12
mA
Input Frequency³
F_i
Pin Inductance¹
L_pin
V_DD = 3.3 V
14.31818
7
MHz 3
nH
1
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
5
pF
1
6
pF
1
C_INX
X1 & X2 pins
5
pF
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms 1,2
Modulation Frequency
Triangular Modulation
30
33
kHz 1
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
15
ns
1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
10
us
1
Tfall_CPU_Stop#
PD# fall time of
5
ns
1
Trise_CPU_Stop#
PD# rise time of
5
ns
2
SMBus Voltage
V_DD
2.7
5.5
V
1
Low-level Output Voltage
V_OL
@ I_PULLUP
0.4
V
1
Current sinking at V_OL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time³
I_PULLUP
T_RI2C
4
(Max VIL - 0.15) to (Min VIH + 0.15)
mA
1
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time³
T_FI2C (Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency}
accuracy on PLL outputs.
IDT^TM Progammable Timing Control Hub^TM for Next Gen P4^TM Processor
5
701J—01/25/10