ICS932S421B Datasheet, PDF (6/23 Pages) Integrated Device Technology – PCIe Gen2 and QPI Clock for Intel-Based Servers

ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDD_A
-
3.3V Logic Input Supply _{VDD_In}
-
Voltage
Storage Temperature
Ts
-
Ambient Operating Temp Tambient
-
Case Temperature
Tcase
-
Input ESD protection HBM ESD prot
-
1_{Guaranteed by design and characterization, not 100% tested in production.}
MIN
TYP
GND - 0.5
-65
0
2000
MAX
V_DD + 0.5V
V_DD + 0.5V
150
70
115
UNITS
V
V
°_C
°C
°C
V
Notes
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input-
High Voltage
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
V_SS - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up
resistors
-5
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
-200
V_{IH_FS}
3.3 V +/-5%
0.7
V_DD + 0.3
V
0.8
V
5
uA
uA
uA
V_DD + 0.3
V
Low Threshold Input-
Low Voltage
V_{IL_FS}
3.3 V +/-5%
V_SS - 0.3
0.35
V
Operating Supply Current
Powerdown Current
I_DD3.3OP
I_DD3.3PD
Full Active, C_L = Full load;
all diff pairs driven
all differential pairs tri-stated
350
mA
70
mA
12
mA
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Modulation Frequency
Tdrive_PD
Tfall_PD
Trise_PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_STAB
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-
assertion of PD to 1st clock
Triangular Modulation
CPU output enable after
PD de-assertion
PD fall time of
PD rise time of
14.31818
7
5
6
5
1.8
30
33
300
5
5
MHz
nH
pF
pF
pF
ms
kHz
us
ns
ns
SMBus Voltage
V_DD
2.7
Low-level Output Voltage
V_OL
@ I_PULLUP
Current sinking at
V_OL = 0.4 V
I_PULLUP
4
SCLK/SDATA
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
5.5
V
0.4
V
mA
1000
ns
300
ns
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.}
Notes
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IDT^TM PCIe Gen2 and QPI Clock for Intel-Based Servers
6
1340G—01/26/10