ICS932S421B Datasheet, PDF (16/23 Pages) Integrated Device Technology – PCIe Gen2 and QPI Clock for Intel-Based Servers

ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
SMBus Table: CPU Frequency Control Register
Byte 11
Pin #
Name
Bit 7
-
CPU N Div8
Bit 6
-
CPU N Div9
Bit 5
-
CPU M Div5
Bit 4
-
CPU M Div4
Bit 3
-
CPU M Div3
Bit 2
-
CPU M Div2
Bit 1
-
CPU M Div1
Bit 0
-
CPU M Div0
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
M Divider Programming
bit (5:0)
Type
0
1
PWD
RW
X
RW The decimal representation of X
RW ^{M and N Divider in Byte 11 and} X
RW ^{12 will configure the CPU VCO} X
frequency. Default at power up
RW _{= latch-in or Byte 0 Rom table.} X
RW _{VCO Frequency = 14.318 x}
X
RW [NDiv(9:0)+8] / [MDiv(5:0)+2] X
RW
X
SMBus Table: CPU Frequency Control Register
Byte 12
Pin #
Name
Bit 7
-
CPU N Div7
Bit 6
-
CPU N Div6
Bit 5
-
CPU N Div5
Bit 4
-
CPU N Div4
Bit 3
-
CPU N Div3
Bit 2
-
CPU N Div2
Bit 1
-
CPU N Div1
Bit 0
-
CPU N Div0
Control Function
N Divider Programming
Byte12 bit(7:0) and
Byte11 bit(7:6)
Type
0
1
PWD
RW
X
RW The decimal representation of X
RW ^{M and N Divider in Byte 11 and} X
RW ^{12 will configure the CPU VCO} X
frequency. Default at power up
RW _{= latch-in or Byte 0 Rom table.} X
RW _{VCO Frequency = 14.318 x}
X
RW [NDiv(9:0)+8] / [MDiv(5:0)+2] X
RW
X
SMBus Table: CPU Spread Spectrum Control Register
Byte 13
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
CPU SSP7
CPU SSP6
CPU SSP5
CPU SSP4
CPU SSP3
CPU SSP2
CPU SSP1
CPU SSP0
Control Function
Spread Spectrum
Programming bit(7:0)
Type
0
1
PWD
RW
X
RW
X
RW
X
RW ^{These Spread Spectrum bits in} X
Byte 13 and 14 will program the
RW
spread pecentage of CPU
X
RW
X
RW
X
RW
X
SMBus Table: CPU Spread Spectrum Control Register
Byte 14
Pin #
Name
Bit 7
-
Bit 6
-
CPU SSP14
Bit 5
-
CPU SSP13
Bit 4
-
CPU SSP12
Bit 3
-
CPU SSP11
Bit 2
-
CPU SSP10
Bit 1
-
CPU SSP9
Bit 0
-
CPU SSP8
Control Function
Reserved
Spread Spectrum
Programming bit(14:8)
Type
0
1
PWD
0
RW
X
RW
X
RW _{These Spread Spectrum bits in} X
RW Byte 13 and 14 will program the X
RW ^{spread pecentage of CPU}
X
RW
X
RW
X
IDT^TM PCIe Gen2 and QPI Clock for Intel-Based Servers
16
1340G—01/26/10