ICS932S421B Datasheet, PDF (20/23 Pages) Integrated Device Technology – PCIe Gen2 and QPI Clock for Intel-Based Servers

ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
PD De-assertion
PD
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tstable
<1.8mS
Tdrive_PwrDwn#
<300µS, >200mV
Test Clarification Table
Comments
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FS_C./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FS_C
FS_B/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B6b6.
If test mode is invoked by B6b6, only B6b7
is used to select HI-Z or REF/N
FS_B/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
HW
FS_C/TEST FS_B/TEST
_SEL
_MODE
HW PIN HW PIN
0
X
1
0
1
0
1
1
SW
TEST
ENTRY REF/N or
BIT
HI-Z
B6b6 B6b7 OUTPUT
0
X NORMAL
X
0
HI-Z
X
1
REF/N
X
0
REF/N
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
IDT^TM PCIe Gen2 and QPI Clock for Intel-Based Servers
20
1340G—01/26/10