ICS932S203 Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – Frequency Generator with 133MHz Differential CPU Clocks

ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
X
X
X
X
X
X
X
X
Name
48MHz_USB
48MHz_USB
48MHz_DOT
48MHz_DOT
-
-
-
-
PWD
0
0
0
0
0
0
0
0
Type
RW
RW
RW
RW
-
-
-
-
Description
USB edge rate cntrol
USB edge rate cntrol
DOT edge rate control
DOT edge rate control
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
X
X
X
X
X
X
X
X
Name
Vendor ID Bit0
Vendor ID Bit1
Vendor ID Bit2
Vendor ID Bit3
Revision ID Bit0
Revision ID Bit1
Revision ID Bit2
Revision ID Bit3
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
PWD
1
0
0
0
X
X
X
X
Type
R
R
R
R
R
R
R
R
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Description
Revision ID values will be based on
individual device's revision
IDT^TM Frequency Generator with 133MHz Differential CPU Clocks
6
0601G—01/26/10