ICS932S203 Datasheet, PDF (15/18 Pages) Integrated Circuit Systems – Frequency Generator with 133MHz Differential CPU Clocks

ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
PD# - Assertion (transition from logic "1" to logic "0")
When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be
held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref,
and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid
CPU frequencies 66, 100, 133, 200MHz.
Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one
clock cycle to complete.
Power Down Assertion of Waveforms - Buffered Mode
0ns
PD#
CPUT 100MHz
CPUC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCI 33MHz
USB 48MHz
REF 14.318MHz
25ns
50ns
PD# Functionality
CPU_STOP# CPUT
1
Normal
0
iref * Mult
CPUC
Normal
Float
3V66
66MHz
Low
66MHz_OUT
PCICLK_F
PCICLK
PCICLK
USB/DOT
48MHz
66MHz_IN 66MHz_IN 66MHz_IN 48MHz
Low
Low
Low
Low
IDT^TM Frequency Generator with 133MHz Differential CPU Clocks
15
0601G—01/26/10