ICS932S203 Datasheet, PDF (14/18 Pages) Integrated Circuit Systems – Frequency Generator with 133MHz Differential CPU Clocks

ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
3V66
3V66 3V66 (5:0) pin to pin skew
0
PCI
PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 0
3V66 to PCI
S_3V66-PCI 3V66 (5:0) leads 33MHz PCI
1.5
1_{Guaranteed by design, not 100% tested in production.}
TYP
MAX UNITS
500 ps
500 ps
3.5 ns
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
IDT^TM Frequency Generator with 133MHz Differential CPU Clocks
14
0601G—01/26/10