ICS932S203 Datasheet, PDF (4/18 Pages) Integrated Circuit Systems – Frequency Generator with 133MHz Differential CPU Clocks

ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Byte 0: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
-
55
40
Name
FS0
FS1
Bit 3 34 PCI_STOP#³
Bit 4
-
Bit 5 35 3V66_1/VCH
Bit 6
-
Bit 7
-
Spread
Enabled
PWD
1
X
X
X
1
0
0
0
Type
R
R
R
RW
RW
Description
(Reserved)
Reflects the value of FS0 pin sampled on power up
Reflects the value of FS1 pin sampled on power up
Hardware mode: Reflects the value of PCI_STOP#
pin sampled on PWD
(Reserved)
VCH Select 66MHz/48MHz
0=66MHz, 1=48MHz
(Reserved)
0=Spread Off, 1=Spread On
Byte 1: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
52, 51
49, 48
45, 44
52, 51
49, 48
45, 44
53, 54
43
Name
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
CPUCLKT3
CPUCLKC3
MULTSEL0
PWD
1
1
1
0
0
0
1
X
Type
RW
RW
RW
-
-
-
RW
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Reserved
Reserved
Reserved
0=Disabled 1=Enabled
Reflects the current value of MULTSEL0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP
conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix
these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
IDT^TM Frequency Generator with 133MHz Differential CPU Clocks
4
0601G—01/26/10