843034I-06 Datasheet, PDF (6/25 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

ICS43034I-06 Data Sheet
FEMTOCLOCK™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD M
H
X
X
Inputs
N S_LOAD
X
X
S_CLOCK
X
Conditions
S_DATA
X Reset the PLL.
L
L
Data Data
X
L
↑
Data Data
L
L
H
XX
L
L
H
XX
↑
X
X
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
H
XX
↓
L
Data M divider and N output divider values are latched.
L
H
XX
L
X
X Parallel or serial input do not affect shift registers.
L
H
XX
H
↑
Data S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
256
M8
128
M7
64
M6
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
600
27
0
0
0
0
1
1
0
1
0
•
•
•
•
•
•
•
•
•
•
•
666.6
30
0
0
0
0
1
1
1
1
0
•
•
•
•
•
•
•
•
•
•
•
711.04 (default)
32
0
0
0
1
0
0
0
0
0
733.3
33
0
0
0
1
0
0
0
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal, CLK, or REF_CLK input frequency of
22.22MHz.
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
*NA2 *NA1 *NA0
N Divider Value
0
0
1
2
0
1
1
4
1
0
0
5
*NOTE: Programming for Bank A and Bank B.
Output Frequency (MHz)
Minimum
Maximum
300
375
150
187.5 (default)
120
150
843034I-06 REVISION B 8/20/15
6
©2015 Integrated Device Technology, Inc.