843034I-06 Datasheet, PDF (15/25 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

ICS43034I-06 Data Sheet
FEMTOCLOCK™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
CLK/nCLK INPUTS
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left floating. We recommend that
there is no trace attached.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_CLK INPUT
For applications not requiring the use of the reference clock, it can
be left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 7A and 7B show two different layouts which are recom-
mended only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock com-
ponent process variations.
3.3V
3.3V
R3
R4
125
125
3.3V
Z_o = 50
+
Z_o = 50
R1
84
_
R2
84
Input
FIGURE 7A. LVPECL OUTPUT TERMINATION
843034I-06 REVISION B 8/20/15
15
FIGURE 7B. LVPECL OUTPUT TERMINATION
©2015 Integrated Device Technology, Inc.