843034I-06 Datasheet, PDF (4/25 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

ICS43034I-06 Data Sheet
FEMTOCLOCK™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 2. PIN DESCRIPTIONS
Number
1, 41, 42,
43, 44, 45,
47, 48
2, 3, 4
5
6
7
8, 14
9, 10
11
12, 24
13
15, 16
17
18, 19
20
21
22
23
25
26
27
28
29
30, 31
Name
M8, M0, M1,
M2, M3,
M4, M6, M7
RESERVED
OE_REF
OE_A
OE_B
V
CC
NA0, NA1
NA2
V
EE
TEST
FOUTA0, nFOU-
TA0
V
CCO_A
FOUTB0,
nFOUTB0
V
CCO_B
REF_OUT
V
CCO_REF
nc
MR
S_CLOCK
S_DATA
S_LOAD
V
CCA
SEL0, SEL1
Type
Description
Input
Pulldown
M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
Reserve
Input
Input
Input
Power
Input
Input
Power
Output
Reserved pins. Do not connect.
Pulldown
Output enable. Controls enabling and disabling of REF_OUT output.
LVCMOS/LVTTL interface levels.
Pullup
Output enable. Controls enabling and disabling of FOUTA0, nFOUTA0
outputs. LVCMOS/LVTTL interface levels.
Pullup
Output enable. Controls enabling and disabling of FOUTB0, nFOUTB0
outputs. LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup _{Determines output divider value as defined in Table 4C,}
Pulldown ^{Function Table. LVCMOS/LVTTL interface levels.}
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Output
Differential output for the synthesizer. LVPECL interface levels.
Power
Output supply pin for FOUTA0, nFOUTA0.
Output
Differential output for the synthesizer. LVPECL interface levels.
Power
Output
Power
Unused
Input
Input
Input
Input
Power
Input
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_OUT output.
No connect.
Active High Master Reset. When logic HIGH, forces the internal PLL to
a reset condition which holds the VCO at the minumum value. When
Pulldown logic LOW, the internal dividers and the outputs are enabled. Assertion
of MR does not affect loaded M, N, S and T values. LVCMOS/LVTTL
interface levels.
Pulldown
Clocks in serial data present at S_DATA input into the shift register on
the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Pulldown
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Pulldown
Controls transition of data from shift register into the dividers. LVC-
MOS/LVTTL interface levels.
Analog supply pin.
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
32
REF_CLK
33, 34
XTAL_IN0,
XTAL_OUT0
35, 36
XTAL_IN1,
XTAL_OUT1
Continued on next page...
Input
Input
Input
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN0 is the input,
XTAL_OUT0 is the output.
Crystal oscillator interface. XTAL_IN1 is the input,
XTAL_OUT1 is the output.
843034I-06 REVISION B 8/20/15
4
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