843034I-06 Datasheet, PDF (12/25 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

ICS43034I-06 Data Sheet
FEMTOCLOCK™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The 843034I-06
provides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V , V and V should be
CC
CCA
CCO_X
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 2
illustrates this for a generic V pin and also shows that V requires
CC
CCA
that an additional10Ω resistor along with a 10µF bypass capacitor
be connected to the V pin.
CCA
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
CC
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/
CC
R1 = 0.609.
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
843034I-06 REVISION B 8/20/15
12
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