843034I-06 Datasheet, PDF (2/25 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

ICS43034I-06 Data Sheet
FEMTOCLOCK™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation
using a 22.22MHz crystal. Valid PLL loop divider values for differ-
ent crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The 843034I-06 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 22.22MHz crystal provides a 22.22MHz phase detector
reference frequency. The VCO of the PLL operates over a range of
600MHz to 750MHz. The output of the M divider is also applied to
the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The 843034I-06 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M
and NA inputs are passed directly to the M divider and N output
dividers. On the LOW-to-HIGH transition of the nP_LOAD input,
the data is latched and the M and N dividers remain loaded until
the next LOW transition on nP_LOAD or until a serial event oc-
curs. As a result, the M and NA bits can be hardwired to set the
M divider and NA output divider to a specific default state that
will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the M divider
is defined as follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown
in Table 4B to program the VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 22.22MHz reference
are defined as 26 ≤ M ≤ 33. The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and NA output divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and NA output divide values
are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD
is held HIGH, data at the S_DATA input is passed directly to the M
divider and NA output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and NA bits and
test bits T1 and T0. The internal registers T0 and T1 determine the
state of the TEST output as follows:
T1 T0
00
01
10
11
TEST Output
LOW
S_Data, Shift Register Output
Output of M divider
Same frequency as FOUTA0
843034I-06 REVISION B 8/20/15
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
2
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