ICS9P936 Datasheet, PDF (5/12 Pages) Integrated Device Technology – Low Skew Dual Bank DDR I/II Fan-out Buffer

ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
Timing Requirements VDDQ2.5/1.8 = 1.8 V +/- 0.1V
T_A = 0 - 70°C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated)
SPECIFICATION
PARAMETER
SYMBOL CONDITIONS
-40
MAX UNITS
Max clock frequency
freq_op
125
400
MHz
Application Frequency Range
Input clock duty cycle
freq_App
d_tin
160
400
MHz
40
60
%
CLK stabilization
T_STAB
15
µs
Switching Characteristics (VDDQ2.5/1.8 = 1.8V +/- 0.1V) (see note 1)
T_A = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 1.8 V +/- 0.1V (unless otherwise stated)
SPECIFICATION
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS
Period jitter
T_{jit (per)}
Period jitter
-40
40 ps
Half-period jitter
T_{(jit_hper)}
Half period jitter
-60
60 ps
Cycle to Cycle
T_cyc-T_cyc
Cycle to Cycle jitter
-40
40 ps
Dynamic Phase Offset
T_(DPO)
-50
50 ps
Static Phase Offset
T_(SPO)
-50
0
50 ps
Output to Output Skew
t_skew
DDR(0:5)
40 ps
Output Duty Cycle
Output clock slew rate
t_duty
47
t_sl(i)
Measured from 20% to 80% of
VDDQ
1.5
53 ps
3 V/ns
1. Switching characteristics guaranteed for operating frequency range
IDT^TM/ICS^TM Low Skew Dual Bank DDR I/II Fan-out Buffer
5
1084C 12/03/09