ICS9P936 Datasheet, PDF (1/12 Pages) Integrated Device Technology – Low Skew Dual Bank DDR I/II Fan-out Buffer

DATASHEET
Low Skew Dual Bank DDR I/II Fan-out Buffer
ICS9P936
Description
Dual DDR I/II fanout buffer for VIA Chipset
Output Features
• Low skew, fanout buffer
• SMBus for functional and output control
• Single bank 1-6 differential clock distribution
• 1 pair of differential feedback pins for input to output
synchronization
• Supports up to 2 DDR DIMMs
• 266MHz (DDRI 533) output frequency support
• 400MHz (DDRII 800) output frequency support
• Programmable skew through SMBus
• Individual output control programmable through SMBus
Key Specifications
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time for DDR outputs: 650ps - 950ps
• DUTY CYCLE: 47% - 53%
• 28-pin SSOP/TSSOP package
• RoHS compliant packaging
Pin Configuration
AVDD2.5 1
AGND 2
28 GND
27 ^VDDQ2.5/1.8
BUF_INT 3
26 AVDD2.5
BUF_INC 4
25 ^AGND
DDRT0 5
24 DDRT5
DDRC0 6
23 ^DDRC5
DDRT1 ₇
22 GND
DDRC1 ₈
21 ^VDDQ2.5/1.8
GND 9
VDDQ2.5/1.8 ₁₀
FB_OUTT 11
FB_OUTC ₁₂
20 ^DDRT4
19 DDRC4
18 ^DDRT3
17 DDRC3
DDRT2 13
16 SDATA
DDRC2 14
15 SCLK
28-SSOP & TSSOP
Funtional Block Diagram
BUF_INC
BUF_INT
SCLK
SDATA
Control
Logic
FB_OUTC
FB_OUTT
DDRC (5:0)
DDRT (5:0)
IDT^TM/ICS^TM Low Skew Dual Bank DDR I/II Fan-out Buffer
1084C 12/03/09