ICS841654I Datasheet, PDF (5/17 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR

ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
Units
MHz
Ω
pF
TABLE 6A. LVCMOS AC CHARACTERISTICS, V_DD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
f_MAX
t_R / t_F
odc
Output Frequency REF_OUT
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Minimum
0.60
49
Typical
25
Maximum
1.80
51
Units
MHz
ns
%
TABLE 6B.
HCSL
AC
CHARACTERISTICS,
V=
DD
V
DDOA
=V
DDOB
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
f_MAX
Output Frequency
VCO/5
100
VCO/4
125
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
100MHz,
(1.875MHz - 20MHz)
125MHz,
(1.875MHz - 20MHz)
0.44
0.44
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3
tsk(o)
Output Skew;
NOTE 2, 3
QAx/nQAx,
QBx/nQBx
t_L
V_HIGH
V_LOW
V_OVS
V_UDS
V_rb
V_CROSS
ΔV_CROSS
PLL Lock Time
Voltage High
Voltage Low
Max. Voltage, Overshoot
Min. Voltage, Undershoot
Ringback Voltage
Absolute Crossing Voltage
Total Variation of V_CROSS over all
edges
125MHz
650
700
-150
-0.3
200
t_R / t_F
Output Rise/Fall Time
QAx/nQAx,
QBx/nQBx
measured between
0.175V to 0.525V
100
Δt_R /Δt_F Rise/Fall Time Variation
odc
Output Duty Cycle
QAx/nQAx,
QBx/nQBx
48
NOTE: All specifications are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
35
100
100
950
150
0.3
0.2
550
160
700
125
52
Units
MHz
MHz
ps
ps
ps
ps
ms
mV
mV
V
V
V
mV
mV
ps
ps
%
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
5
ICS841654AGI REV. A APRIL 17, 2008