ICS841654I Datasheet, PDF (11/17 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR

ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
SCHEMATIC LAYOUT
Figure 4 shows an example of ICS841654I application
schematic. In this example, the device is operated at V =
CC
3.3V. The 18pF parallel resonant 25MHz crystal is used.
The C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. For different board layout, the C1 and
C2 may be slightly adjusted for optimizing frequency
accuracy. One example of HCSL and one example of
LVCMOS terminations are shown in this schematic. The
decoupling capacitors should be located as close as possible
to the power pin.
VDD
R8
VDD
VD D
VDD
C5
0.1u
VDD OA
VCC OA
C7
.1uf
nREF_OE
BY PASS
REF_SEL
U1
1
2
VDD
3 ^REF_OUT
4
5
6
7
8
GND
QA0
nQA0
VDDOA
GND
9 ^QA1
10
11
12
13
14
nQA1
nR EF _OE
BY PASS
REF_IN
REF_SEL
VDDA
10
VDDA
C1
0.1u
C2
10u
ICS841654I
I R EF
28
27
FSEL0 ₂₆
FSEL1
QB0
nQB0
VDDOB
GND
25
24
23
22
21
QB1 ₂₀
nQB1
MR / nOE
VDD
XTAL_IN
XTAL_OUT
19
18
17
16
15
GND
R4
475
FSEL0
FSEL1
MR/nOE VDD
VD D
C6
0.1u
X1
C3
25MHz
27pF
18pF
Logic Control Input Examples
C4
Set Logic
Set Logic
27pF
VDD _{Input to} VDD _{Input to}
'1'
'0'
RU1
1K
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
REF _OU T
R1 33
Zo = 50
R2 33
R5 33
Zo = 50
TL2
Zo = 50
TL3
R6
R7
50
50
VDD OB
VCCOB
C8
.1uf
VDD=3.3V
VDDOA=3.3V
VDDOB=3.3V
Zo = 50
TL4
Zo = 50
TL5
R12 R13
50
50
LVCMOS
+
-
Using for PCI Express
Add-In Card
HCSL Termination
+
-
Using for PCI Express
Point-to-Point
Connection
FIGURE 4. ICS841654I SCHEMATIC LAYOUT
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
11
ICS841654AGI REV. A APRIL 17, 2008