ICS841654I Datasheet, PDF (10/17 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR

ICS841654I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS841654I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
X1
18pF Parallel Crystal
XTAL_OUT
C1
27p
XTAL_IN
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
series resistance (Rs) equals the transmission line impedance.
In addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
VVCDDC
V^VCDDC
R1
Ro
Rs
.1uf
Zo = 50
XTAL_I N
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
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ICS841654AGI REV. A APRIL 17, 2008