English
Language : 

ICS831742I Datasheet, PDF (5/18 Pages) Integrated Device Technology – Maximum input/output clock frequency
ICS831742I Data Sheet
4:2 DIFFERENTIAL CLOCK/DATA MULTIPLEXER
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
tj
(PCIe Gen 1)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
tREFCLK_HF_RMS Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
tREFCLK_LF_RMS Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
Test Conditions
ƒ= 100MHz, 100MHz Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 100MHz, 100MHz Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ= 100MHz, 100MHz Input
Low Band: 10kHz - 1.5MHz
ƒ= 100MHz, 100MHz Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum Typical
10
1
0.05
0.2
Maximum
21
2.5
0.2
0.8
PCIe Industry
Specification
86
3.1
3.0
0.8
Units
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. Measurements performed with a PCI Express compliant input source. For additional information,
refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
ICS831742AGI JULY 10, 2012
5
©2012 Integrated Device Technology, Inc.