ICS831742I Datasheet, PDF (11/18 Pages) Integrated Device Technology – Maximum input/output clock frequency

ICS831742I Data Sheet
4:2 DIFFERENTIAL CLOCK/DATA MULTIPLEXER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 2A to 2E show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an IDT Open
Emitter HiPerClockS LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
CLK
nCLK
Differential
R1
R2
84Ω
84Ω
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
2.5V
*R3 33
Zo = 50Ω
Zo = 50Ω
*R4 33
HCSL
R1
50
*Optional – R3 and R4 can be 0Ω
3.3V
CLK
nCLK
Differential
R2
Input
50
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
ICS831742AGI JULY 10, 2012
11
©2012 Integrated Device Technology, Inc.