843034-06 Datasheet, PDF (5/24 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET
TABLE 2. PIN DESCRIPTIONS, CONTINUED
Number
Name
Type
Description
37
CLK
Input Pulldown Non-inverting differential clock input.
38
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input.V /2 default when left floating.
CC
Parallel load input. Determines when data present at M8:M0 is loaded into
39
nP_LOAD Input Pulldown M divider, and when data present at NA2:NA0 is loaded into the N output
dividers. LVCMOS/LVTTL interface levels.
40
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
46
M5
Input
Pullup
M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance REF_OUT
Test Conditions
Minimum
5
Typical
4
51
51
7
Maximum
12
Units
pF
kΩ
kΩ
Ω
REVISION B 8/17/15
5
FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer