843034-06 Datasheet, PDF (14/24 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET
CRYSTAL INPUT INTERFACE
The 843034-06 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 5 below
were determined using a 18pF parallel resonant crystal and were
chosen to minimize the ppm error. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
X1
18pF Parallel Crystal
C1
27pF
XTAL_IN
C2
27pF
XTAL_OUT
FIGURE 5. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 6. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS signals, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω.
VDD
VDD
R1
Ro
Rs
.1uf
Zo = 50
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 6. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
REVISION B 8/17/15
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FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer