843034-06 Datasheet, PDF (3/24 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET
TABLE 1. SSM OPERATION
SS Bit Pattern
Operation
SS3
SS2
SS1
SS0
Mode
%
0
0
0
0
off
0
0
0
0
1
center ±0.25
0
0
1
0
center ±0.25
0
0
1
1
center ±0.85
0
1
0
0
center ±0.85
0
1
0
1
center ±1.45
0
1
1
0
center ±1.45
0
1
1
1
center ±1.7
1
0
0
0
off
0
1
0
0
1
down
-0.25
1
0
1
0
down
-0.25
1
0
1
1
down
-0.75
1
1
0
0
down
-0.75
1
1
0
1
down
-1.25
1
1
1
0
down
-1.25
1
1
1
1
down
-1.5
NOTE: SS modulation frequency is approximately 32kHz using
reference frequency of 22.22MHz, providing a VCO frequency of
666.66MHz.
SPREAD SPECTRUM MODULATION
The 843034-06 offers the option of a spread spectrum modulated
output clock. The spread spectrum is controlled via 4 bits in the
serial bit stream. These four bits configure the SSM to be enabled
and the amount of spread modulation to be selected. See Table
1 for the definition of the four bits. The four bits are added at the
beginning of the serial data stream and are labeled SS3, SS2, SS1
and SS0. The initial state of SS3, SS2, SS1 and SS0 is 0, 0, 0, 0
which places the 843034-06 in the mode of spread spectrum off.
Additionally, a parallel load will result in spread spectrum modulation
being off. The 843034-06 offers down-spread or center-spread using
triangle-wave modulation. NOTE: PLL operation not guaranteed for
M >31 when using center spread.
POWER-UP OPERATION
The 843034-06 has internal power–up reset circuitry that initiates
the phase lock loop to automatically acquire lock on power-up. On
power-up the M/N values for the feedback and output dividers will be
acquired from the M and N pins if nP_Load is held Low. If nP_Load
is High during power-up, M/N values are indeterminate. The M/N
values may be changed by either changing the values on the M/N
pins when nP_LOAD is low or with a serial load when nP_LOAD is
high and S_LOAD is low.
MR PIN OPERATION
Any time there is a change in the input frequency, either due to an
external change or a change in the SEL pins, the MR pin must go
high and low to relock to the new input frequency. A change in the
M feedback divider by either a serial or parallel load will also cause
a relock to the new input frequency.
REVISION B 8/17/15
3
FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer