843034-06 Datasheet, PDF (1/24 Pages) Integrated Device Technology – FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

FemtoClock™ Multi-Rate 3.3V LVPECL
Frequency Synthesizer
843034-06
DATA SHEET
GENERAL DESCRIPTION
The 843034-06 is a general purpose, low phase noise LVPECL
synthesizer which can generate frequencies for a wide variety of
applications. The 843034-06 has a 4:1 input multiplexer from which
the following inputs can be selected: one differential input, one
single-ended input, or one of two crystal oscillators, thus making
the device ideal for frequency translation or frequency generation.
The 843034-06 has dual LVPECL outputs that may be programmed
for ÷2, ÷4 or ÷5 of the VCO frequency. The 843034-06 also supplies
a buffered copy of the reference clock or crystal frequency on the
single-ended REF_OUT pin which can be enabled or disabled
(disabled by default). The output frequency can be programmed
using either a serial or parallel programming interface. This device
supports Spread Spectrum Clocking (SSC) for EMI reduction.
BLOCK DIAGRAM
FEATURES
• Dual differential 3.3V LVPECL outputs
• 4:1 Input Mux:
One differential input
One single-ended input
Two crystal oscillator interfaces
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 120MHz to 375MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 600MHz to 750MHz
• Supports Spread Spectrum Clocking (SSC)
• Parallel or serial interface for programming feedback divider
and output dividers
• RMS phase jitter at 166.6MHz, using a 22.222MHz crystal
(12kHz to 30MHz): 1.33ps (typical), SSC - Off
• 3.3V supply mode
• 0°C to 75°C ambient operating temperature
• Available in lead-free (RoHS 6) package
OE_A ^Pullup
VCO_SEL ^Pullup
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
OSC
OSC
CLK ^Pullup
nCLK ^{Pullup/Pulldown}
REF_CLK ^Pulldown
SEL1 ^Pulldown
SEL0 ^Pulldown
001 ÷2
011 ÷4
100 ÷5
00
FOUTA0
nFOUTA0
01
0
Phase _{VCO 1}
10
Detector
11
÷M
V_{CCO_A}
V_{CCO_B}
FOUTB0
nFOUTB0
PIN ASSIGNMENT
OE_B ^Pullup
MR ^Pulldown
OE_REF ^Pulldown
S_LOAD ^Pulldown
S_DATA ^Pulldown
S_CLOCK ^Pulldown
nP_LOAD ^Pulldown
M8:M0 ^{M0:M4 M6:M8 Pulldown, M5 Pullup}
NA2:NA0 ^{NA2 Pulldown, NA1:0 Pullup}
V_{CCO_REF}
REF_OUT
Configuration
Interface
Logic
TEST
843034-06 REVISION B 8/17/15
1
©2015 Integrated Device Technology, Inc.