8V97051 Datasheet, PDF (34/56 Pages) Integrated Device Technology – Dual Differential Outputs

8V97051 DATA SHEET
Table 12K. Register 7: 1-Bit SCLKE. Function Description
Name
Description
Factory Default
Sclke
SCLKE
1
Function
0 = Output Data in a Read Cycle on a Rising Edge of SCLK
1 = Output Data in a Read Cycle on a Falling Edge of
SCLK
Table 12L. Register 7: 1-Bit READBACK_ADDR. Function Description¹
Name
Description
Function
Rd_Addr[3:1]
READBACK_ADDR
000 = Register 0
001 = Register 1
010 = Register 2
011 = Register 3
100 = Register 4
101 = Register 5
110 = Register 6
111 = Register 7
NOTE 1. In order to Read a register, the user must write to Register 7 first and set the SPI_R_WN Bit to 1 (READ) and indicate the address
of the register to read in the READBACK_ADDR Bit (Bits[D6:D4]).
Table 12M. Register 7: 1-Bit SPI_R_WN. Function Description¹
Name
Description
Factory Default
Function
SPI_R_WN
SPI_R_WN
0
0 = WRITE
1 = READ
NOTE 1. Writing this bit to a ‘1’ will allow the user to read back the register selected in READBACK_ADDR on the next 32 SCLK cycle. This
bit will revert back to ‘0’ once it is written with ‘1’ and will not retain the ‘1’ value.
Table 12N. Register 7: 3-Bit Control Bits. Function Description¹
Name
Description
Function
CB[3:1]
CONTROL BITS
111 = Register 7 is programmed
NOTE 1. The user has to set CB[3:1] to 111 in order to write to Register 7.
LOW POWER WIDEBAND FRACTIONAL RF SYNTHESIZER / PLL
34
REVISION 3 07/30/15